1. Field of the Invention
The present invention relates to a deposition method for a transition-metal-containing dielectric.
2. Description of the Related Art
Although in principle applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology.
Memory cells of a DRAM device each comprise a capacitor for storing information encoded as electric charge retained in the capacitor. A reliable operation of the memory cells demands for a minimal capacitance of the capacitors and a sufficiently long retention time of the charge in the capacitors.
There is a major interest to further reduce the lateral dimensions of structures of a DRAM, at present 45 nm are envisaged. Therefore, it becomes necessary to compensate the shrinking lateral dimensions of the capacitors by increasing the k-value of the dielectric layer. The use of high k-dielectric layers demands for development of new deposition techniques, which can be combined with standard processing steps like high-temperature annealing steps. In particular a heat assisted migration of oxides formed on metallic electrodes into the dielectric layers must be inhibited as these oxides tend to reduce the band gap of the dielectric materials and to increase leakage currents, which cause a short retention time.